Semiconductor devices, especially those designed to block high voltages and conduct large currents in high power applications, are subjected to powerful electrical forces and electromagnetic fields at the molecular level. Further, these devices may be subjected to high temperatures during fabrication and operation. These forces, fields, and temperatures can damage the molecular structure of the various layers and regions within the device, as well as the interface between these various layers or regions. Such damage leads to device failures as well as degraded performance over time. For field effect devices employing a metallized gate that is separated from the body of the device by a dielectric layer, the dielectric layer and the interface between the dielectric layer and the body are particularly vulnerable. As such, there is a need for a gate dielectric for a field effect device that is less vulnerable to the forces and fields that are generated in high voltage and current applications as well as the potentially damaging temperatures associated with fabrication and operation.